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Header: DTCO: Co-optimising Design and Technology at the Heart of Advanced SemiconductorsThe so-called Design-Technology Co-Optimization (DTCO) approach has become a central element in the development of next-generation integrated circuits and associated electronic architectures.
In the design of modern integrated circuits, performance optimisation no longer relies solely on advances in manufacturing processes or on improvements in design methodologies. These two dimensions are now closely interconnected. It is in this context that the Design-Technology Co-Optimization (DTCO) approach has emerged, aiming to coordinate technological development and circuit design from the earliest phases of a project.
DTCO is a co-development methodology that seeks to closely align manufacturing technology and circuit design in order to maintain the industrial viability, performance and energy efficiency of integrated circuits in advanced technology nodes.
An evolution of the traditional design model
Historically, the development of an integrated circuit followed a relatively sequential logic. Foundries would develop a new manufacturing process and subsequently publish a PDK (Process Design Kit) containing electrical models and design rules. Design teams would then use these elements to develop circuits.
As the industry has progressed towards increasingly advanced technology nodes, this separation has become less effective. Technology choices now directly influence circuit architectures and design strategies. DTCO therefore relies on a collaborative approach in which the manufacturing process, design rules and circuit architecture are adjusted jointly.
The objective is to achieve balanced trade-offs between several key parameters in semiconductor engineering: performance, energy consumption, chip area and the ability to manufacture the circuit reliably at industrial scale.
A more constrained technological context
The importance of DTCO has increased with the introduction of advanced transistor technologies and more complex lithography techniques. Transistor architectures such as FinFET and later Gate-All-Around transistors have enabled continued component scaling, but they also introduce stricter manufacturing constraints. Similarly, the adoption of Extreme Ultraviolet Lithography modifies design parameters and imposes specific layout rules.
In these technological environments, design margins are reduced and the interactions between transistor geometry, interconnect routing and process variability become more sensitive. Decisions taken at the process level can influence the density of logic cells or the electrical performance of circuits. Conversely, certain circuit architectures may require adaptations to the manufacturing process.
An iterative approach between process and design
DTCO relies on a series of feedback loops between process development teams and circuit designers. Design rules—such as spacing between patterns, grid orientation or contact structures—can be adjusted to better match the real capabilities of the manufacturing process.
At the same time, standard-cell libraries and analogue blocks are adapted to take advantage of the available technological characteristics. This optimisation aims to improve integration density or energy efficiency while maintaining a level of reliability compatible with high-volume production.
Modelling tools and evolving PDKs play an important role in this process. They enable designers to simulate early the impact of certain technological decisions and to guide design choices even before the process is fully finalised. Design prototypes and simulations thus support the joint evaluation of several criteria, notably performance, power consumption and chip area—often grouped under the acronym PPA (Power, Performance, Area)—as well as variability and manufacturing yield.
Broader collaboration across the semiconductor ecosystem
Implementing DTCO involves several stakeholders across the integrated circuit development chain. Foundries contribute to defining and evolving the manufacturing process. Circuit design teams leverage these technologies to develop logical or analogue architectures. Meanwhile, providers of electronic design automation (EDA) tools supply the simulation, place-and-route and verification environments required to support these optimisations.
In some cases, system architects also participate in the process in order to align circuit-level design choices with the functional requirements of the final product.
DTCO and the evolution towards system-level optimisation
DTCO forms part of a broader trend towards joint optimisation at multiple levels of electronic design. It is often associated with System-Technology Co-Optimization (STCO), which extends this logic to the scale of the complete system.
While DTCO mainly focuses on devices, cells and circuits, STCO considers broader aspects such as system-on-chip architectures, advanced interconnects, chiplet architectures or three-dimensional circuit stacking (3D-IC). This approach becomes particularly relevant in a context where the overall performance of a product depends as much on packaging and system architecture as on the transistor itself.
Sustaining the progress of integrated circuits
The widespread adoption of DTCO illustrates how the semiconductor industry is adapting to the physical and economic limits of continued scaling. By bringing together teams responsible for process development and those in charge of circuit design, this approach seeks to sustain improvements in performance and energy efficiency while preserving the industrial viability of advanced semiconductor technologies.
Article edited by Youssef Belgnaoui, a journalist specialising in industrial technologies.
