Anritsu Corporation Launches New High Speed CXL Compliance Testing Solution

Anritsu Corporation has expanded its testing portfolio by introducing a dedicated Compute Express Link evaluation solution for its bit error rate tester platform. This software and hardware integration addresses the validation requirements of semiconductor developers working on high-bandwidth data center architectures and memory expansion modules.

High-Speed Signal Integrity Challenges in Next-Generation Data Centers
The rapid adoption of artificial intelligence and high-performance computing driving data center architectures requires low-latency, high-bandwidth communication between central processing units, graphics pyramids, and memory pools. Compute Express Link (CXL) technology serves as an open standard interconnect protocol designed to run over the physical layer of Peripheral Component Interconnect Express (PCIe) to provide coherent memory access.

The transition between protocol generations introduces severe signal integrity challenges. While CXL 2.0 operates on the PCIe 5.0 physical layer utilizing Non-Return-to-Zero (NRZ) signaling at 32 gigabaud (GBd), CXL 3.x transitions to the PCIe 6.0 physical layer. This shift introduces Pulse Amplitude Modulation 4-level (PAM4) signaling at 64 gigatransfers per second (GT/s). PAM4 signaling packs twice as much data into the same time slot by utilizing four voltage levels instead of two, but this reduces the signal-to-noise ratio by more than 9.5 dB, necessitating precise physical layer verification.

Automated Testing Mechanisms and Error Analysis
The Signal Quality Analyzer-R MP1900A functions as a high-performance bit error rate tester (BERT) to isolate physical layer anomalies from protocol-level behavior. In multi-lane environments required to secure enterprise bandwidth, distinguishing whether a bit error stems from channel degradation or protocol state machine errors is critical for debugging early-stage silicon.

The platform combines a high-quality pulse pattern generator (PPG) output with a highly sensitive error detector (ED) input. To simulate real-world operational stress and ensure reproducible compliance verification, the system injects specific deterministic distortions. These include sinusoidal jitter (SJ), random jitter (RJ), spread spectrum clocking (SSC), bounded uncorrelated jitter (BUJ), as well as common-mode and differential-mode interference (CM-I/DM-I).

Through an integrated graphical user interface, engineers can build automated test sequences that execute link training and status state machine (LTSSM) analysis. The testing software reproduces complex link state transitions, including Jump and Loop scenarios, allowing hardware designers to evaluate device performance under both standard operation and worst-case stress conditions. This multi-lane simultaneous evaluation capability reduces hardware validation cycles and accelerates product time-to-market.

Additional Context: Technical Specifications and Competitive Benchmarking
This solution joins the market of high-end validation systems, where bit error rate measurement reliability at 64 GT/s serves as the primary differentiator. The MP1900A competes directly with established platforms such as the Keysight M8000 series and the Tektronix BSX system.

A technical comparison highlights equivalent performance parameters regarding PAM4 signal generation and jitter injection capabilities. Both the Anritsu MP1900A with its CXL extension and the Keysight M8000 series (specifically the M8040A) support a maximum PAM4 data rate of up to 64 GBd or 128 Gbps. In terms of integrated protocol compliance, the Anritsu platform covers CXL 1.1, 2.0, and 3.x alongside PCIe Gen1-6, matching the Keysight system which supports CXL 1.1, 2.0, and 3.0 alongside PCIe Gen1-6. For stress testing, both systems provide simultaneous injection of sinusoidal jitter, random jitter, spread spectrum clocking, and bounded uncorrelated jitter, while also featuring integrated common-mode and differential-mode voltage noise interference sources.

While Keysight provides deep integration with EDA simulation tools to close the design cycle from concept to physical prototype, the Anritsu approach focuses on test sequence execution efficiency through its graphical user interface. The capability of the MP1900A to link protocol logic analysis functions directly with physical PAM4 error rate detection within a unified system reduces the requirement for external oscilloscopes during foundational troubleshooting of the LTSSM state machine.

Edited by Evgeny Churilov, Induportals Media - Adapted by AI.

www.anritsu.com