Xilinx Launches Industry’s First SmartNIC Platform Bringing Turnkey Network, Storage and Compute Acceleration to Cloud Data Centers

Also unveils OCP 3.0 form factor XtremeScale Ethernet adapter; proof of concept for world's first FPGA-based OCP Accelerator Module.

Xilinx, announced the industry’s first SmartNIC platform delivering true convergence of network, storage and compute acceleration functions on a single device. The Alveo U25 SmartNIC is designed to bring the greater efficiency and lower TCO benefits of SmartNICs to cloud service providers, telcos, and private cloud data center operators struggling with increasing networking demands and rising costs.

The U25 combines a highly optimized SmartNIC platform with a powerful and flexible FPGA-based engine that supports full programmability and turnkey accelerated applications. The U25 delivers a comprehensive SmartNIC platform to address the industry’s most challenging demands and workloads such as SDN, virtual switching, NFV, NVMe-oF, electronic trading, AI inference, video transcoding, and data analytics.

In addition, Xilinx announced its first XtremeScale Ethernet adapter card in the Open Compute Project (OCP) Spec 3.0 form factor and a proof of concept for the world’s first FPGA-based OCP Accelerator Module (OAM).

“The SmartNIC market is forecast to surpass $600M and comprise 23 percent of the worldwide Ethernet adapter market by 2024,” according to Baron Fung, research director at Dell’Oro Group. “As cloud service providers scale capacity upwards, they are increasing their deployment of SmartNICs to free up valuable CPU cores for business applications, optimizing server utilization. The telco service providers, another market with strong growth potential, are looking to integrate SmartNICs from the core to the edge of the network for applications such as NFV and AI inferencing. FPGA-based SmartNICs such as the Alveo U25 are well positioned to address this growing market opportunity.”

Converged SmartNIC Platform for Accelerated Clouds

As network port speeds continue to increase, tier 2 and 3 cloud service providers, telcos, and private cloud data center operators are facing mounting networking challenges and costs. Still, the significant R&D investments required to develop and deploy SmartNICs have hindered broader adoption. The Alveo U25 SmartNIC platform addresses these barriers by providing true plug-and-play capabilities that make SmartNICs accessible for more widespread deployments.

Powered by Xilinx’s industry-leading FPGA technology, the Alveo U25 SmartNIC provides higher throughput and a far more adaptable engine than SoC-based NICs to allow cloud architects to accelerate a wide range of functions and applications quickly. The platform enables ‘bump-in-the-wire’ network, storage, and compute offload and acceleration functions for maximum efficiency by avoiding unnecessary data movements and CPU processing. This dramatically reduces the CPU burden and reclaims resources to run more applications.

Embedded ARM processors provide unique and critical control plane processing to support emerging bare metal server use cases. The baseline NIC delivers ultra-high throughput, small packet performance, and low-latency. Standard full-featured NIC functionality and drivers, including Onload^® application acceleration software, can reduce latency up to 80 percent and improve transmission control protocol (TCP)-based server application efficiency by up to 400 percent in cloud-based applications.

“Today’s cloud infrastructures suffer from critical data bottlenecks caused by server I/O,” said Donna Yasay, vice president of marketing, Data Center Group at Xilinx. “With up to 30 percent of data center compute resources allocated for networking I/O processing, overhead continues to grow along with CPU cores. Xilinx is addressing the challenges resulting from the increased demands on networking by providing an easier to deploy SmartNIC with turnkey accelerated applications and out-of-the-box capabilities that go far beyond fundamental networking.”

Out-of-the-Box Accelerated Applications for Faster Time-to-Market

The Alveo U25 SmartNIC platform enables turnkey accelerated applications that make it easier for non-tier-1 cloud data center operators to deploy SmartNICs and quickly reap the benefits. The U25 SmartNIC supports turnkey applications from both Xilinx and independent software vendors. The programming model supports high-level network programming abstractions such as HLS and P4, as well as compute acceleration frameworks such as the Vitis unified software platform to enable Xilinx and third party accelerated applications.

The first out-of-the-box accelerated application available on the Alveo U25 SmartNIC is support for Open vSwitch (OVS) offload and acceleration. The plug-and-play solution will offload over 90 percent of OVS processing from the server to improve packet throughput by over 5X. Future turnkey solutions from Xilinx are planned for security functions such as IPSec, SSL/TLS, AES-256/128, and distributed firewall as well as AI inference acceleration.

The Alveo U25 SmartNIC is currently sampling with early access customers. General availability is expected in the third calendar quarter of 2020.

First OCP 3.0 Ethernet Adapter and OCP Accelerator Module

Xilinx also unveiled the new XtremeScale X2562 10/25Gb Ethernet adapter card based on the OCP Spec 3.0 form factor. Designed for high-performance electronic trading environments and enterprise data centers, the X2562 features sub-microsecond latency and high throughput with ultra-scale connectivity for real-time packet and flow information to thousands of virtual NICs. The X2562 is currently sampling and will be generally available in the second calendar quarter of 2020.

Additionally, Xilinx announed a proof of concept for the world’s first FPGA-based Open Compute Accelerator Module (OAM). Based on the Xilinx^® UltraScale+ VU37P FPGA with 8GB of HBM memory and compliant with Open Accelerator Infrastructure (OAI), the mezzanine-based card supports seven 25Gbps x8 links to enable rich inter-module system topologies for distributed acceleration.

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