Keysight Partners with 800 Gigabit Ethernet Ecosystem to Demonstrate Physical Design Validation Solution

Enables testing forward error correction performance at high data rates in next generation, hyperscale data center ecosystem.

Keysight Technologies, Inc. (NYSE: KEYS), a leading technology company that delivers advanced design and validation solutions to help accelerate innovation to connect and secure the world, today announced a demonstration of a physical design validation solution featuring high speed Ethernet partners in the quad small form factor pluggable double density (QSFP-DD800) ecosystem.

Network equipment manufacturers (NEMs) in the high-speed Ethernet ecosystem are working to meet the demand for higher speeds and traffic density in hyperscale data centers. To meet the power and performance demands for high-speed network solutions, the QSFP-DD Multisource Agreement (MSA) group announced a hardware revision 6.0 to introduce the QSFP-DD800 specification and Common Management interface Specification (CMIS) 5.0 in May 2021.

The multi-company demonstration is first to showcase this form factor running full line rate, Ethernet speeds based on the IEEE 802.3ck 100G Pulse Amplitude Modulation 4-level (PAM4) electrical lanes. Along with Keysight, the demonstration includes partners in the DD800 ecosystem including host board connectors from Amphenol and link partner from system company Cisco. These leading companies are active contributing members of the QSFP-DD MSA.

"The QSFP-DD form factor continues to evolve to support next generation data centers supporting signal integrity, thermal performance, and port density," said Scott Sommers, co-chairman of the QSFP-DD MSA and Molex director of Industry Standards. "Keysight's new G800 builds on the industry momentum supporting QSFP-DD infrastructure."

"We are pleased to see the QSFP-DD800 ecosystem expanding with test solutions such as the G800 from Keysight," said Mark Nowell, Cisco Fellow. "This capability is critical to Cisco when developing products with 800G QSFP-DD800 ports."

Demonstration Highlights New High Data Rate Multiple Channel FEC Test Solution
The new Keysight G800 advanced bit error ratio test (BERT) and forward error correction (FEC) error density and performance analysis system is the first test solution designed specifically for testing all Ethernet speeds based on 112G electrical lanes, including Ethernet Technology Consortium 800GE and IEEE 802.3 400GE, 200GE and 100GE. The G800 integrates with the Keysight M8040A bit error ratio tester (BERT) and the Keysight UXR-Series oscilloscope to provide insights into FEC constraints for physical design validation and compliance.

Keysight's latest test solution enables NEMs and hyperscale data center providers to evaluate interoperability and FEC performance with error analysis such as patented BERT inferred FEC. It features an easy-to-see system overview of FEC performance across all Ethernet speeds in real-time, in 112Gb/s electrical lanes.

"Higher-speed Ethernet is a complex multiple channel environment. NEMs need visibility into all Ethernet lanes to detect and correlate meaningful errors to achieve the best performance," said Jerry Pepper, Keysight Fellow. "Keysight is first to deliver these test capabilities, integrated with our BERT and UXR real-time oscilloscope. Together, they enable NEMs to gain unprecedented insights into their higher data rate implementation challenges for the hyperscale data centers of the future."

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