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Upgraded MP1900A PCI Express® 5.0 Receiver and USB 3.2 x2-Lane Tests

Anritsu Corporation is pleased to announce the sales launch of its Signal Quality Analyzer-R MP1900A series with upgraded PCI Express® 5.0 Receiver and USB 3.2 x2-lane Test functions.

Upgraded MP1900A PCI Express® 5.0 Receiver and USB 3.2 x2-Lane Tests

These PCI 5.0 CEM - function upgrades provide an effective Sequence Editor for debugging Link Training as well as an optional accessory for compensating return path loss. Additionally, the USB 3.2 x2-lane measurement specified by the new standard for USB Type-C® connectors is also supported as a software option.

The all-in-one MP1900A supporting both PCI Express and USB standards helps resolve the measurement challenges of these new standards while contributing to customers’ evaluation efficiency and making best use of their investment in test equipment.

Background

The rollout of commercial 5G services supports high-speed communications using large data to facilitate rapid advances in the latest technologies, including IoT and AI. At the same time, the interfaces of transmission equipment, such as servers and storage, in data centers forming the backbone of this technology revolution are being upgraded to PCI Express for faster transmission of larger data traffic. Evaluation of PCI Express 5.0 is challenging, especially when there are problems with transitioning to the DUT test mode at Link Training. Moreover, BER measurements at Compliance Tests may be impossible when the return path loss is large.

In addition, the standard for USB Type-C connectors built into various digital equipment, such as smartphones, tablet PCs, etc., as interfaces for high-speed transmission of large video and data files has been upgraded to USB 3.2 supporting 10 Gbit/s x 2 lanes, which increases test challenges, such as the time required to measure two lanes compared to earlier 1-lane measurements.

Product Outline
The MP1900A is a high-performance BERT supporting Receiver Tests of high-speed computer and data communications interfaces, such as PCIe, USB, Thunderbolt, 400 and 800GbE, etc.

As well as a dedicated GUI optimized for debugging PCI Express 5.0 Link Training challenges, an optional software Sequence Editor function has also been developed. When the PCI Express 5.0 Compliance Test DUT return channel path loss is large, the BER can still be measured by using the accessory Re-Driver Set to compensate for loss.

In addition, the USB 3.2 Gen1/Gen2 x1/x2-lane DUT Receiver Test is supported by using the BERT 2ch options with the USB 3.2 x2 Link Training software option for lane identification using two-way Link Training and BER measurement after transitioning to the test mode, which can be fully automated using GRL’s automation software.

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