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Fraunhofer IPMS Introduces 10G TSN Endpoint IP Core
New IP Core enables deterministic Ethernet communication at up to 10 Gbit/s for automotive, industrial and safety-critical networks.
www.fraunhofer.de

Deterministic high-speed Ethernet is becoming a key requirement in automotive electronics, industrial automation and safety-critical systems. Rising sensor data volumes and centralized computing architectures demand higher bandwidth combined with precisely predictable timing. Fraunhofer Institute for Photonic Microsystems IPMS addresses this requirement with a new 10G TSN Endpoint IP Core designed for real-time Ethernet networks operating at up to 10 Gbit/s.
The 10G TSN Endpoint (EP) expands the existing Time-Sensitive Networking (TSN) IP Core portfolio of Fraunhofer IPMS. Compared to the previous 1G TSN IP Cores, the new solution increases data throughput by a factor of ten while maintaining deterministic network behavior. It is intended for applications requiring maximum bandwidth, nanosecond-level synchronization accuracy and reliable, time-controlled data transmission.
Nanosecond-accurate time synchronization
The 10G TSN-EP IP Core implements hardware-accelerated synchronization in accordance with IEEE 802.1AS-2020 (gPTP). This enables time synchronization accuracy below 10 nanoseconds within Ethernet networks, ensuring stable and consistent time bases even at high transmission speeds.
The IP Core supports key TSN standards including IEEE 802.1Qav (audio/video traffic shaping), IEEE 802.1Qbv (time-aware scheduling), IEEE 802.1Qci (per-stream filtering and policing) and IEEE 802.1CB (Frame Replication and Elimination for Reliability, FRER). These mechanisms enable deterministic latency control, bandwidth reservation and fault-tolerant transmission within high-speed Ethernet infrastructures.
FPGA and ASIC integration support
To accelerate implementation, Fraunhofer IPMS provides Linux driver packages and reference designs. These support native XGMII as well as widely used 10G interfaces such as 10G-BASE-R, SFI and XFI, commonly implemented on FPGA platforms including AMD Xilinx devices.
The 10G TSN-EP IP Core is designed for established FPGA and ASIC target platforms, allowing integration into customer-specific hardware architectures while reducing development time. The availability of reference implementations shortens design cycles and facilitates faster time to market for real-time Ethernet solutions.
Application scenarios in automotive and industry
In modern in-vehicle networks, the 10G TSN-EP IP Core can serve as a deterministic backbone for advanced driver assistance systems (ADAS), infotainment domains and centralized vehicle computers. High bandwidth combined with precise time synchronization supports sensor fusion and high-resolution video data transport.
In sensor systems, the IP Core enables low-jitter, low-loss transmission of video, radar and lidar streams, including simultaneous multistream operation. For industrial automation, it supports scalable real-time Ethernet networks for synchronized motion control, robotics and image-processing production lines. Predictable end-to-end latency budgets improve operational reliability in complex manufacturing environments.
Expansion toward higher-speed TSN architectures
According to Fraunhofer IPMS, the 10G TSN Endpoint marks the starting point for a new generation of high-speed TSN IP Cores. Within the CeCas research project, the institute is developing a high-performance computing platform for highly automated vehicles and is evaluating 25G TSN solutions.
In addition to the 10G TSN-EP IP Core, a 10G TSN switched endpoint and a 10G TSN switch are currently under development and are scheduled to become available later this year.
www.ipms.fraunhofer.com

