Anritsu Releases New PCI Express Gen 7.0 Receiver Test Solution

Anritsu Corporation has expanded the capabilities of its Signal Quality Analyzer-R MP1900A to support receiver testing for the upcoming PCI Express 7.0 specification. The updated Bit Error Rate Tester system addresses compliance evaluation requirements for networking hardware, data centers, and high-performance computing architectures utilizing data transfer rates up to 128 GT/s.

Signal Calibration and Error Rate Verification at 128 GT/s
The transition to PCI Express 7.0 introduces PAM4 signaling at ultra-high frequencies, which significantly reduces timing margins and increases susceptibility to noise. To validate receiver performance under worst-case operating conditions, the modified test platform synthesizes precise stressed test signals by injecting controlled levels of random jitter, sinusoidal jitter, and bounded uncorrelated jitter into the data stream.

Automating the calibration of these complex test signals represents a critical shift in verification workflows. By interfacing directly with high-bandwidth real-time oscilloscopes from partner manufacturers, the system executes automated calibration routines and subsequent jitter tolerance measurements. This closed-loop automation eliminates manual adjustments, ensuring repeatable test conditions that align with the rigorous compliance criteria defined in the Base Specification during early-stage physical layer validation.

Architectural Features of the Physical Layer Test System
The underlying hardware architecture of the Signal Quality Analyzer-R MP1900A is designed to handle multiple generations of high-speed serial buses, including legacy PCI Express revisions, USB, Thunderbolt, DisplayPort, and 800 GbE. For PCI Express 7.0 applications, the instrument leverages low intrinsic random jitter and a high Signal-to-Noise-and-Distortion Ratio to prevent the test equipment itself from degrading the measurement margin. The primary objective of the system is to provide a standardized, reproducible environment for PCI-SIG compliance testing, allowing hardware developers to isolate receiver sensitivity issues and verify error-correction performance prior to final product certification.

Additional Context: Technical Specifications and Competitive Benchmarking
The deployment of PCI Express 7.0 at 128 GT/s over PAM4 signaling requires test equipment capable of generating accurate symbols with a Nyquist frequency of 32 GHz. In this technical segment, the primary competitive alternative is the Keysight M8040A High-Performance BERT system.

When evaluating these platforms for 128 GT/s testing, the critical performance indicators are intrinsic jitter generation and clock recovery tracking bandwidth. The Anritsu MP1900A architecture utilizes integrated hardware slots to minimize signal path lengths, achieving an intrinsic random jitter typically below 150 femtoseconds RMS. In comparison, the Keysight M8040A offers modular configurations that achieve similar low-jitter performance but require specific external hardware components to scale up to the full 128 GT/s PAM4 requirement.

Furthermore, automated calibration time remains a primary differentiator; while Keysight utilizes proprietary Link Training and Status State Machine capabilities to automate receiver testing, Anritsu relies on deep software integration with third-party real-time oscilloscopes (such as those from Tektronix and Teledyne LeCroy) to distribute processing loads and accelerate the calibration of complex physical layer stress profiles.

Edited by Evgeny Churilov, Induportals Media - Adapted by AI.

www.anritsu.com