Direct 800V DC Rack Power Conversion

High-density artificial intelligence computing clusters require unprecedented levels of electrical power, pushing legacy rack-level voltage architectures past practical distribution limits. Microchip Technology and Navitas Semiconductor have developed a joint reference design for data center server racks that converts an 800V DC bus directly down to 6V DC for processor power delivery.

The Transition to High-Voltage Rack Distribution
Standard enterprise servers traditionally operate on 12V DC or 48V DC backplane distribution. However, dense clusters running high-power graphical processing units draw hundreds of amperes per server tray. Distributing megawatts of power at 48V DC introduces severe resistive conduction losses (I²R) along the copper busbars, requiring thick conductors that restrict airflow and increase weight.

To resolve these physical constraints, hyperscale facilities are adopting 800V DC distribution aligned with the Open Compute Project standards. Stepping up the rack distribution voltage reduces current by a factor of more than sixteen for an equivalent load, allowing smaller conductor cross-sections, lowering system-level thermal dissipation, and streamlining the digital supply chain for data center power equipment.

Single-Stage Direct Power Conversion Topology
Converting 800V DC down to intermediate and point-of-load rails has historically required a multi-stage approach, typically stepping down from 800V DC to 48V or 50V DC before a second converter drops the voltage to sub-10V chip levels. Each intermediate stage introduces compounding switching and conduction penalties that depress end-to-end efficiency.

The joint reference design integrates an 800V-to-6V DC power delivery board that eliminates the intermediate stage entirely. The primary stage employs sixteen NV6034 650V, 17 mΩ GaNFast power transistors configured in a stacked half-bridge topology. The wide-bandgap gallium nitride switches are housed in DFN 8x8 dual-side-cooled packages, which lower junction-to-case thermal resistance and permit continuous high-power operation under high switching frequencies. Operating at a 1 MHz switching frequency, the converter targets up to 96% peak efficiency at full electrical load while achieving a power density of 2,100 W/in³.

Physical Packaging and Transient Performance
Minimizing parasitic impedance is critical when driving low-voltage, high-current processor rails that experience rapid load transients. The power delivery board is built with an ultra-low profile, approximately 20% thinner than a standard smartphone.

This low height allows electrical engineers to position the power conversion hardware directly adjacent to the accelerator board. Placing the output stages close to the processor package shortens trace lengths, minimizes line inductance, improves transient load response, and reduces voltage drop during rapid dynamic current swings.

Deterministic Digital Control and Post-Quantum Security
High-frequency switched-mode conversion at 1 MHz requires sub-nanosecond timing precision to maintain zero-voltage switching across variable loads. Control for the reference design is handled by Microchip dsPIC33AK digital signal controllers. Specifically, the dsPIC33AK256MPS306 processor features a 200 MHz 32-bit core paired with a double-precision floating-point unit, 78 ps high-resolution pulse width modulators, and multiple 12-bit analog-to-digital converters sampling at rates up to 40 MSPS.

Beyond core power conversion, connected power supplies within the broader automotive data ecosystem and open hyperscale infrastructure represent potential attack surfaces for unauthorized firmware manipulation. To establish system protection, the architecture incorporates a Microchip TA100 CryptoAuthentication integrated circuit as a hardware root of trust. The security controller handles secure boot verification, message authentication code generation, Transport Layer Security key exchange, and protected over-the-air firmware updates. The system libraries also support Commercial National Security Algorithm Suite 2.0 post-quantum cryptographic standards to protect against future quantum-assisted cryptanalysis.

The complete reference design, including hardware, embedded software, and design documentation, will be presented at the 2026 OCP Global Summit from October 12 to 15, 2026, in San Jose, California.

Additional Context
This section details technical specifications and competitive benchmarking not included in the original product announcement.

Hyperscale operators are shifting server rack specifications from the legacy Open Rack standard version 2 (12V) and Open Rack standard version 3 (48V) to 400V DC and 800V DC architectures driven by the Open Compute Project Open Rack version 4 guidelines. At 100 kW to 300 kW per rack, 48V busbars demand excessive copper volume, whereas 800V DC distribution reduces distribution current to manageable levels below 400 A total.

In standard data center implementations, direct 800V-to-POL conversion competes against two-stage architectures that use high-voltage isolated bus converters (stepping 800V down to 48V at approximately 97.5% to 98% efficiency) followed by secondary multiphase buck or resonant switched-capacitor modules (stepping 48V down to core voltages at 94% to 96% efficiency). The combined efficiency of two-stage systems typically tops out between 91.5% and 94%. By achieving 96% peak efficiency in a single direct stage, the 800V-to-6V GaN topology eliminates intermediate losses and saves board area, though it requires advanced semiconductor devices capable of handling severe voltage step-down ratios without compromising duty-cycle resolution.

Edited by Evgeny Churilov, Induportals Media - Adapted by AI.

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