Infineon debuts RISC-V based AURIX RC1 microcontrollers for software-defined vehicles
The hybrid MCU/MPU platform scales across automotive domains, integrating advanced edge AI, multi-Gigabit Ethernet, and post-quantum cryptography readiness.
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Infineon Technologies has unveiled the AURIX™ RC1, a fundamentally new microcontroller (MCU) platform engineered for the next generation of software-defined vehicles (SDVs) and Physical AI applications. Showcased at electronica 2026 in Munich, the RC1 marks a strategic technological shift as Infineon’s first automotive MCU to leverage the open-standard RISC-V instruction set architecture. By providing a common, highly scalable hardware foundation, the platform aims to replace fragmented, domain-specific point solutions, accelerating software development and hardware integration across zone, body, chassis, powertrain, and driver assistance systems. Engineering samples are scheduled for the first half of 2027.
Hybrid processing architecture and DRIVECORE ecosystem
Designed to handle the massive computational loads of centralized car computers, the AURIX RC1 scales from traditional microcontroller tasks to complex hybrid MCU/MPU (microprocessor) architectures. Depending on the specific application lineup, the silicon integrates up to twelve 32-bit processing cores, a dedicated parallel processing unit for edge AI, and up to 40 megabytes of embedded memory, with plans to introduce 64-bit microprocessor capabilities in future variants. To streamline the transition from legacy architectures, Infineon supports the hardware with its new DRIVECORE software ecosystem. This environment offers AI-assisted migration tools, virtual prototyping for pre-silicon development, and pre-integrated bundles for AUTOSAR and open-source operating systems.
Post-quantum security and in-vehicle networking
Meeting the stringent requirements of autonomous and connected mobility, the platform supports the highest automotive functional safety level (ASIL D). It also features advanced cybersecurity mechanisms compliant with ISO/SAE 21434 and the Cyber Resilience Act, incorporating hardware-level crypto-agility that is prepared for future post-quantum cryptography standards. For high-speed in-vehicle data routing, the RC1 supports high-bandwidth communication protocols such as CAN-XL, 10BASE-T1S, and multi-Gigabit Ethernet. Selected devices also feature integrated BRIGHTLANE™ Ethernet switching and hardware-accelerated data routing, significantly reducing external component counts and offloading the main application processors.
Infineon redefines real-time compute and control for software-defined vehicles and Physical AI with new AURIX™ RC1
Additional Context: RISC-V instruction sets and Zonal E/E architectures
This section details microprocessor architecture and automotive network topologies not included in the original press release.
Unlike proprietary Instruction Set Architectures (ISAs) such as the ubiquitous ARM Cortex—which dominates the current automotive MCU market and requires strict licensing agreements—RISC-V is an open-standard architecture. Its modular nature allows semiconductor manufacturers to implement a standardized base instruction set while adding custom, proprietary extensions (such as specific vector math instructions for AI inference or custom cryptographic accelerators). This provides unprecedented flexibility to tailor silicon for specific automotive workloads while fostering a broader, vendor-agnostic software ecosystem.
The push for chips like the AURIX RC1 is heavily driven by the automotive industry's shift from Domain to Zonal Electrical/Electronic (E/E) architectures. Traditional vehicles utilize decentralized Electronic Control Units (ECUs) categorized by function (e.g., separate ECUs for braking, lighting, and HVAC) connected by massive, heavy wire harnesses. Software-defined vehicles (SDVs) use Zonal Architectures, where powerful central computers handle high-level processing, and "zone controllers" manage all power distribution and data routing for a specific physical location in the car (e.g., the front-left quadrant), regardless of the function. This topology requires microcontrollers capable of mixed-criticality processing—meaning they must utilize hardware-level hypervisors to simultaneously manage a critical ASIL-D braking signal and a low-priority CAN-XL ambient lighting command on the same silicon without any latency or interference.
Edited by an industrial journalist, Lekshman Ramdas, with AI assistance.
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