Ansys Enables Faster, More Reliable Chip Design for Juniper Networks
Ansys’ distributed compute platform and proven hierarchical methodology accelerates Juniper's networking chip design verification.
Juniper Networks, a leader in secure, artificial intelligence (AI)-driven networks, successfully deployed Ansys' software to accelerate production of its high-speed networking chips.
Key Highlights
- Ansys’ SeaScape platform's unique elastic compute architecture eliminates the need for expensive large-memory machines required by legacy tools
- Ansys Chip Power Model (CPM) supports accurate hierarchical power analysis across an entire multi-chip system
Ansys today announced that Juniper Networks, a leader in secure, artificial intelligence (AI)-driven networks, successfully deployed the company’s software to accelerate production of its high-speed networking chips. Ansys helps Juniper achieve highly predictively accurate power integrity signoff in significantly less time with a massively parallelizable design methodology that achieves greater switching coverage and improved reliability.
Networking chips are some of the largest, most complex chips in the semiconductor industry and are vital components in all data transfer applications — including telecommunications, internet switching and high-speed data center hardware. Advanced networking products often require the successful integration of multiple sub-chips coming together to form a single system solution.
Juniper faced several challenges while implementing their latest 7nm high-speed networking product: the capacity to analyze a design with over 60 billion transistors; the ability to ensure reliable dynamic and static voltage drop (DVD) coverage for possible switching scenarios; and the hierarchical support needed to enable full-system analysis across multiple integrated circuits. Juniper chose Ansys® RedHawk-SC™’s distributed processing capabilities to significantly accelerate the power integrity signoff for their newest high-performance networking chips. Ansys’ hierarchical Chip Power Model also facilitated high-fidelity power network co-simulation of the chip and package.
“Despite the increasing size and complexity of our networking solutions, Ansys RedHawk-SC enabled our design teams to deliver outstanding results,” said Debashis Basu, senior vice president, engineering at Juniper Networks. "The software was very easy to distribute in our on-premises cloud via standard memory machines, and its advanced features were crucial in delivering more reliable networking products to market faster.”
Ansys RedHawk-SC leads the industry in power noise and reliability sign off for digital IP and SoC down to 3nm. Its powerful analytics quickly identify weaknesses and allow what-if explorations to optimize power and performance. The software’s cloud-optimized architecture enables the speed and capacity needed for full-chip analysis.
"Our comprehensive suite of integrated electronics tools quickly solve the power management challenges inherent in today’s ultra-large and complex chip designs," said John Lee, vice president and general manager of the semiconductor, electronics and optics business unit at Ansys. "Ansys RedHawk-SC plays a big part in Juniper’s overarching, cloud-enabled strategy for delivering higher speed and capacity. Our broad platform of multiphysics signoff analysis products consistently help our customers optimize their design performance, while reducing the project and technology risks at the leading edge of semiconductor technology."
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