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Keysight technologies News
KEYSIGHT INTRODUCES CHIPLET PHY DESIGNER FOR SIMULATING D2D TO D2D PHY IP SUPPORTING THE UCIE™ STANDARD
Chiplet PHY simulator addresses the effects of forward clocking with single-ended signalling and higher bit error rate on die-to-die interconnect performance of chiplets.
Chiplet PHY Designer simulates the UCIe specification for D2D physical layer interconnect.
Keysight Technologies introduces Chiplet PHY Designer, the latest member in its family of high-speed digital design and simulation tools that provides die-to-die (D2D) interconnect simulation, which is a key step in verifying performance for heterogeneous and 3D integrated circuit (IC) designs commonly referred to as chiplets. The new electronic design automation (EDA) tool is the industry's first to provide in-depth modelling and simulation capabilities that enable chiplet designers to rapidly and accurately verify that their designs meet specifications of the Universal Chiplet Interconnect Express™ (UCIe™) standard.
Key features of the Chiplet PHY Designer physical-layer simulator include:
Keysight Technologies introduces Chiplet PHY Designer, the latest member in its family of high-speed digital design and simulation tools that provides die-to-die (D2D) interconnect simulation, which is a key step in verifying performance for heterogeneous and 3D integrated circuit (IC) designs commonly referred to as chiplets. The new electronic design automation (EDA) tool is the industry's first to provide in-depth modelling and simulation capabilities that enable chiplet designers to rapidly and accurately verify that their designs meet specifications of the Universal Chiplet Interconnect Express™ (UCIe™) standard.
Key features of the Chiplet PHY Designer physical-layer simulator include:
- Supports UCIe physical layer standard – automated parsing of signals following the standard naming conventions, automated connections between multiple dies through package interconnects, standard driven simulation setup such as speed grade, and intuitive measurement setup through specialized probe component.
- Measurement of voltage transfer function (VTF) – precisely computes a VTF to ensure UCIe specification compliance and analyzes system bit error rate (BER) down to 1e-27 or 1e-32 levels. Measures eye diagram height, eye width, skew, mask margin, and BER contour.
- Analysis of forwarded clocking to accurately capture the asynchronous clocking behavior.
- See Chiplet PHY Designer at DesignCon
Keysight will be demonstrating Chiplet PHY Designer in its DesignCon booth #1039 at the Santa Clara Convention Center from January 31-February 1, 2024.
For more information, visit: Chiplet PHY Designer
For more information, visit: Chiplet PHY Designer
