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Siemens Adds Agentic AI to Chip Verification
New workflows automate RTL checks, debugging and planning while remaining compatible with existing EDA environments and cloud-based development infrastructures.
www.sw.siemens.com
Growing chip complexity from chiplets, 3D integration and software-defined functions increases verification effort across semiconductor design teams. Siemens introduced the Questa One Agentic Toolkit, extending its Questa™ One verification software with autonomous AI-driven workflows for integrated circuit design and verification.
Closing the verification productivity gap
Verification increasingly dominates development time in advanced semiconductor projects such as automotive processors, industrial controllers and communication SoCs. The toolkit introduces domain-specific agentic AI — software agents that plan and execute tasks under user-defined governance limits while keeping engineers in control of approval decisions.
The system automates verification creation, execution and troubleshooting for Register Transfer Level (RTL) development. Instead of separate tools performing isolated steps, the workflows coordinate tasks across planning, checking and debugging, helping teams reach approval stages more reliably within a digital engineering workflow.
Works inside existing design environments
The framework integrates with the Fuse™ EDA AI system and remains compatible with other agent platforms through standardized interfaces. Engineers can operate it through command-line tools or development environments such as VS Code, and it works alongside AI coding assistants including GitHub Copilot, Claude Code, Cursor and Cline.
The architecture connects multiple Siemens verification engines including Questa One Verification IQ, Questa One SFV, Questa One Sim, Tessent™ software for DFT and the Veloce™ CS hardware-assisted verification platform. Model Context Protocols (MCPs) expose verification status data in real time, allowing AI agents to track relationships between specifications, test benches and coverage.
What the agents actually do
The toolkit introduces several specialized agents designed for different verification stages:
- The RTL Code Agent generates synthesizable RTL code from natural language descriptions and checks rule compliance before review.
- The lint agent analyzes existing code and suggests corrections or approval paths.
- The CDC agent configures and evaluates clock-domain-crossing verification for asynchronous logic.
- The Verification Planning Agent builds verification plans from specifications and defines test scenarios.
- The debug agent correlates waveforms, assertions and logs to identify probable failure mechanisms and propose targeted debugging tests.
These agents can decompose verification targets, adapt strategies across runs and accumulate project knowledge while engineers approve key decisions.
Preparing verification flows for large-scale systems
The approach supports scalable semiconductor development where multiple subsystems are verified concurrently, such as automotive electronics and high-performance computing devices. Continuous updates and automated coordination allow teams to maintain consistency across distributed development environments typical of a cloud-based silicon design ecosystem.
The toolkit uses reasoning models based on NVIDIA NIM and NVIDIA Llama Nemotron and incorporates technology developed with domain-expert prompt libraries.
www.siemens.com
Preparing verification flows for large-scale systems
The approach supports scalable semiconductor development where multiple subsystems are verified concurrently, such as automotive electronics and high-performance computing devices. Continuous updates and automated coordination allow teams to maintain consistency across distributed development environments typical of a cloud-based silicon design ecosystem.
The toolkit uses reasoning models based on NVIDIA NIM and NVIDIA Llama Nemotron and incorporates technology developed with domain-expert prompt libraries.
www.siemens.com
