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Keysight Expands PCIe 7.0 Receiver Test Portfolio
Keysight Technologies introduced a PCIe 7.0 receiver test application for validating receiver performance at 128 GT/s in AI, compute, and data center systems.
www.keysight.com
Keysight Technologies announced a new PCIe® 7.0 Receiver (RX) Test application designed to support end-to-end transmitter and receiver validation for next-generation high-speed interconnect applications. The solution addresses receiver validation challenges associated with PCIe 7.0 operation at 128 GT/s.
According to Keysight, the accelerated pace of PCIe base specification releases and the industry transition toward PCIe 7.0 adoption are increasing the complexity of receiver validation. The company stated that engineers face challenges related to limited receiver-specific test equipment and more demanding stress signal calibration requirements.
PCIe 7.0 Receiver Validation at 128 GT/s
Keysight stated that reliable receiver validation testing is necessary to reduce development risk and support interoperability as PCIe 7.0 ecosystems expand. The company said the new receiver test application enables engineers to validate device performance under stressed signal conditions.
The solution combines the Keysight M8050A BERT family with the M8042A 120 GBaud pattern generator and the M8043A error analyzer. According to the company, the hardware platform supports PCIe 7.0 receiver stress testing through signal generation and analysis intended for ASIC validation workflows.
Software for Stress Signal Calibration
Keysight also introduced the N5991PB7A software package to simplify calibration and control of PCIe 7.0 receiver stress signals.
The company stated that the software reduces setup complexity and accelerates receiver validation through automated workflows and calibration processes. Advanced automation capabilities are intended to support more accurate and reliable ASIC receiver characterization.
End-to-End PCIe 7.0 Validation
According to Keysight, the combined hardware and software platform provides a complete PCIe 7.0 receiver test solution for common clock mode validation.
The company stated that the solution is designed to:
- Accelerate receiver bring-up and validation through automated PCIe 7.0 RX workflows
- Reduce compliance risks at 128 GT/s through stressed-signal generation aligned with PCIe specifications
- Complement existing PCIe 7.0 transmitter test solutions to provide end-to-end transmitter-to-receiver validation coverage
Additional Context
PCI Express (PCIe) is a high-speed interface standard widely used for communication between processors, accelerators, storage devices, and networking hardware in computing systems. Each new PCIe generation increases data transfer speeds and bandwidth requirements, creating additional challenges for signal integrity and interoperability testing.
PCIe 7.0 introduces signaling speeds of up to 128 GT/s, increasing the complexity of receiver and transmitter validation. Receiver stress testing is used to evaluate how devices operate under degraded or challenging signal conditions, helping engineers identify weaknesses in ASICs and communication interfaces before deployment.
Bit error ratio testers (BERTs), pattern generators, and error analyzers are commonly used in high-speed digital interface validation to generate stressed signals, analyze receiver performance, and measure error rates under different operating conditions. Automation software is increasingly important in these workflows due to the complexity of calibration and compliance requirements for next-generation interfaces.
Edited by Romila DSilva, Induportals Editor, with AI assistance.
PCI Express (PCIe) is a high-speed interface standard widely used for communication between processors, accelerators, storage devices, and networking hardware in computing systems. Each new PCIe generation increases data transfer speeds and bandwidth requirements, creating additional challenges for signal integrity and interoperability testing.
PCIe 7.0 introduces signaling speeds of up to 128 GT/s, increasing the complexity of receiver and transmitter validation. Receiver stress testing is used to evaluate how devices operate under degraded or challenging signal conditions, helping engineers identify weaknesses in ASICs and communication interfaces before deployment.
Bit error ratio testers (BERTs), pattern generators, and error analyzers are commonly used in high-speed digital interface validation to generate stressed signals, analyze receiver performance, and measure error rates under different operating conditions. Automation software is increasingly important in these workflows due to the complexity of calibration and compliance requirements for next-generation interfaces.
Edited by Romila DSilva, Induportals Editor, with AI assistance.
