Toshiba Ships Test Samples of New Efficient SiC MOSFET

Toshiba Electronic Devices and Storage Corporation begins engineering sample shipments of a new silicon carbide power transistor optimized for high-power artificial intelligence computing environments.

The deployment of high-density artificial intelligence computing infrastructure necessitates advanced electrical architectures to manage accelerating energy consumption. To satisfy the performance parameters of high-power hardware and 800V high-voltage direct current distribution setups, industrial power conversion networks require semiconductor devices featuring reduced thermal generation and optimal switching profiles. The introduction of sample shipments for the TW007D120E silicon carbide power transistor targets these performance benchmarks across enterprise data centers, photovoltaic inverters, uninterruptible power supply topologies, electric vehicle charging infrastructure, energy storage systems, and industrial motor drives.

Optimization of Conduction and Switching Performance
Engineering data confirms that the 1200V silicon carbide metal-oxide-semiconductor field-effect transistor minimizes electrical resistance through a specialized trench-gate architecture. This physical design integrates gate electrodes directly into micro-trenches within the semiconductor substrate, increasing channel density per unit area.

As a result, the device demonstrates a drain-source on-resistance of 7.0 milliohms at a gate-source voltage of 15V and a junction temperature of 25 degrees Celsius. Compared to previous third-generation planar configurations, specifically the TW015Z120C model, the design decreases the specific on-resistance per unit area by approximately 58 percent.

Thermal Management and Package Characteristics
The design mitigates the traditional operational trade-off between conduction losses and switching dynamics. The structural figure of merit, defined as the product of drain-source on-resistance and gate-drain charge, indicates a 52 percent reduction relative to earlier planar components. This optimization yields a total gate charge of 317 nanocoulombs and a gate-drain charge of 33 nanocoulombs under a drain-source voltage of 800V. Lower internal capacitance values, including an input capacitance of 13972 picofarad, reduce energy dissipation during rapid transitions, which directly cuts down on heat generation in continuous switching applications.

To manage thermal dissipation under heavy loads, the component uses a QDPAK surface-mount package designed for top-side cooling. This structural packaging allows direct thermal coupling to an upper heatsink, preventing thermal buildup within the printed circuit board substrate. The electrical configuration handles an absolute maximum continuous drain current of 172 amperes at a case temperature of 25 degrees Celsius, matching the current density needs of compact power conversion modules.

Project Subsidization and Production Timeline
Development of the semiconductor device was completed in connection with project JPNP21029, an industrial initiative subsidized by the New Energy and Industrial Technology Development Organization. Production timelines establish that industrial scaling and mass manufacturing processes are scheduled to begin during fiscal year 2026. Future iterations of the trench-gate platform are planned to expand into automotive powertrain systems and high-capacity industrial equipment to lower carbon dioxide emissions through improved electrical efficiency.

Additional Context: Technical Specifications and Competitive Benchmarking
The performance of the 1200V trench-gate silicon carbide transistor reflects broader industrial shifts toward trench architectures, which overcome the cell-pitch limitations of traditional planar planar field-effect transistors. In the 1200V power semiconductor sector, comparable trench-gate silicon carbide technologies include platforms from manufacturers like Infineon Technologies with their CoolSiC series and Rohm Semiconductor with their third and fourth-generation silicon carbide configurations.

A technical comparison indicates that while early planar devices exhibited higher specific on-resistance per unit area, contemporary trench geometries achieve equivalent or lower internal resistance by aligning the conduction channel along favorable crystal planes of the silicon carbide substrate. The benchmarking parameter of a 7.0 milliohms nominal internal resistance places this device within the top performance tier for discrete surface-mount power devices, matching the low conduction losses of alternative industrial modules. Furthermore, top-side cooling packages like the QDPAK compete directly with specialized configurations such as the TOLT package, both designed to isolate thermal pathways from the circuit board, thereby increasing the safe operating area and power density limits compared to standard back-side cooled D2PAK formats.

Edited by Evgeny Churilov, Induportals Media - Adapted by AI.

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