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Toshiba Launches 80V Power MOSFET for Efficient AI Data Center Power Supplies

New U-MOS11-H-based MOSFET delivers lower power losses, reduced EMI and improved thermal performance for high-density industrial power applications.

  www.global.toshiba
Toshiba Launches 80V Power MOSFET for Efficient AI Data Center Power Supplies

Toshiba Electronic Devices & Storage Corporation has initiated shipments of the TPM1R408RH, an 80V N-channel power MOSFET designed using the U-MOS11-H manufacturing process. The hardware component is engineered to optimize switched-mode power supplies within industrial equipment, specifically targeting the semiconductor supply chain supporting artificial intelligence data centers and communications base stations.

Semiconductor Supply Chain Optimization and Thermal Management
The proliferation of artificial intelligence processing operations requires enhanced power density and minimized electromagnetic interference in facility infrastructure. Energy losses within power supply units directly impact total system consumption and increase the required cooling load. By deploying power semiconductors with balanced conduction and switching loss characteristics, facility operators can improve thermal design and manage the power data ecosystem more effectively.

Resistance Reduction and Voltage Spike Suppression Mechanisms
The TPM1R408RH hardware utilizes an optimized structural design to achieve a maximum drain-source On-resistance of 1.4 milliohms under standard test conditions of 10V gate-source voltage, 50A drain current, and an ambient temperature of 25 degrees Celsius. This metric indicates a 26 percent reduction in resistance compared to the previous generation TPM1R908QM module fabricated on the U-MOS X-H process. Additionally, the component lowers the figure of merit, calculated as drain-source On-resistance multiplied by total gate charge, by approximately 45 percent, shifting from 205.2 milliohm-nanocoulombs to 112 milliohm-nanocoulombs.

The internal device structure also suppresses voltage spikes generated between the drain and source during switching operations. This suppression reduces electromagnetic interference, which consequently minimizes the need for design rework and simplifies the integration of secondary filter and snubber circuits within the power system.

Physical Packaging and Simulation Integration
The component utilizes the SOP Advance E packaging standard, which reduces package resistance by 65 percent and lowers thermal resistance by 15 percent relative to the preceding SOP Advance N format. These physical modifications decrease heat generation and improve dissipation, enabling the development of more compact power supply architectures.

For integration testing, Toshiba provides G0 SPICE models for rapid functional verification and highly accurate G2 SPICE models to replicate transient characteristics. An associated online circuit simulation platform permits engineering teams to verify operational parameters directly through standard web interfaces without requiring localized software installations or device model downloads. The ongoing expansion of this product lineup is intended to reduce overall power consumption in continuous industrial equipment operations.

Additional Context:
This section details technical specifications and competitive benchmarking not included in the original product announcement

In the 80V N-channel power MOSFET sector, competitive components from manufacturers such as Infineon Technologies and onsemi target similar applications in telecommunications and data center power supplies. Infineon OptiMOS 5 and OptiMOS 6 series operating at 80V offer drain-source On-resistance values ranging from 1.2 milliohms to 1.8 milliohms when housed in standard 5x6 millimeter surface-mount packages, which are directly comparable to the SOP Advance format. Similarly, onsemi provides shielded-gate PowerTrench 80V MOSFETs that achieve On-resistance metrics in the 1.5 milliohm range to manage switching losses and heat dissipation. The benchmark criteria for these components uniformly focus on the figure of merit pairing resistance with total gate charge, alongside the thermal resistance of the packaging, as these specific variables dictate the cooling requirements and maximum power density of server power supply units.

Edited by Natania Lyngdoh, Induportals editor, assisted by AI.

www.toshiba.semicon-storage.com

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