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Digital Twin Center Advances Semiconductor Research and Development
STMicroelectronics collaborates with academic and industrial partners to establish a research facility deploying digital infrastructure for semiconductor design and qualification.
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STMicroelectronics is establishing a research and development center at its Castelletto site in Italy to develop digital twins for semiconductor engineering. Working alongside academic institutions such as Politecnico di Milano, research organizations, and industrial suppliers, the initiative targets microelectromechanical systems, silicon photonics, power devices, and automotive integrated circuits.
Engineering Challenges in Physical Silicon Prototyping
Semiconductor design cycles face rising technical complexity, extended verification loops, and escalating wafer fabrication costs. Conventional development workflows rely heavily on iterative physical silicon validation to detect layout errors, process variations, and device-level reliability defects. These sequential learning cycles increase engineering lead times and raise development expenditures across complex multi-domain systems.
Predictive Digital Framework and Technical Roles
To address physical iteration bottlenecks, STMicroelectronics coordinates the development environment while external academic and technology partners contribute algorithmic models and computing methodologies. Politecnico di Milano collaborates on AI models tailored to silicon photonics, while specialized software and equipment suppliers provide simulation interfaces.
The technical architecture couples physics-based numerical modeling, multi-physics simulations, and multivariate anomaly detection with experimental silicon data. Operating on an integrated device manufacturer framework, the digital twin system forms a closed calibration loop:
- Physical characterization data from wafer fabrication continually calibrates the underlying process models.
- Automated simulation tools predict electro-thermal and mechanical interactions prior to mask creation.
- Machine learning algorithms analyze process margins to optimize layout design and qualification schedules.
Implementation Phases and Verification
The deployment follows a two-phase roadmap:
The deployment follows a two-phase roadmap:
- Phase 1 (through 2027): Infrastructure setup, laboratory equipping, and initial proof-of-concept testing. Key demonstrator projects include virtual simulation test automation and digital twin architectures for MEMS accelerometers.
- Phase 2 (subsequent three to five years): Full integration and scaling of the digital engineering architecture across the company's research, development, and testing infrastructure.
The Castelletto facility leverages proximity to the Agrate manufacturing cluster, utilizing existing engineering knowledge in BCD technologies, smart power systems, and advanced packaging.
Industrial Impact
By replacing empirical silicon iterations with verified digital simulations, the collaborative workflow improves first-pass design success, accelerates cycle times, and enhances operational predictability across industrial automation, automotive electronics, and optical communication applications.
Edited by Evgeny Churilov, Induportals Media - Adapted by AI.
www.st.com
Industrial Impact
By replacing empirical silicon iterations with verified digital simulations, the collaborative workflow improves first-pass design success, accelerates cycle times, and enhances operational predictability across industrial automation, automotive electronics, and optical communication applications.
Edited by Evgeny Churilov, Induportals Media - Adapted by AI.
www.st.com
