CEA-Leti Quantum Program Director, Maud Vinet, Shares the Path Towards Full Fault-Tolerant Quantum Computing with Si-Based VLSI Technologies In Plenary Talk at IEDM 2022
CEA-Leti presented three papers at IEDM 2022 detailing its recent advances and future challenges in quantum computing using Si-based qubit devices with FDSOI technologies. A plenary talk presented the path towards scalable quantum computers with silicon technology.
An invited paper presented CEA-Leti’s modelling approach in developing low-temperature FDSOI cryoelectronics and the third contributed paper shared the institute’s success in developing a strategy to perform electrical characterization at a large range of temperatures down to ultra-low temperatures.
Paper No. 1 “Enabling Full Fault Tolerant Quantum Computing with Silicon-Based VLSI Technologies”
In a Dec. 5 plenary session, Maud Vinet, CEA-Leti’s quantum hardware program director, presented CEA-Leti and CNRS’s demonstrations that FDSOI technology enables full fault-tolerant quantum computing leveraging very-large-scale integration (VLSI) fabrication and design techniques. And she called on electrical engineers in collaboration with physicists to turn these demonstrations into practical machines.
Vinet, who now serves as CEO of a recent quantum spinoff from CEA and the French National Centre for Scientific Research (CNRS) called Siquance, said quantum technology’s promise to “launch a computing revolution reaching unchartered computing territories” remains a distant goal in part because “the path towards full fault-tolerant quantum computing is not yet paved”. Quantum’s life-changing applications, in chemistry and energy, for example, could be reached “if we were able to have lots of high-quality physical qubits together with an efficient quantum error correction scheme”.
Potential “life-changing” applications are out of reach because the quantum algorithms necessary to support them require more than 100 perfect qubits to be run typically around millions of operations, the paper reports. “To provide accurate results, this demands a precision below 10-6 … which is way below the precision any of the physical systems used so far to build qubits. As a consequence, quantum error correction is introduced to turn analog quantum computing into a digital quantum regime.”
Shielding computation from inherent quantum noise is critical to achieving the full computational power of quantum computers. “The integration of quantum error correction (QEC) into the quantum computation led to the development of the fault-tolerant quantum computing (FTQC) framework, which is key for the development of a universal, large-scale quantum computer. Currently, topological quantum codes, such as surface codes or triangular color codes, are promising candidates for FTQC,” the paper reports. Several challenges remain to be overcome to integrate QEC in practical systems.
Vinet said full fault-tolerant computing enables implementing algorithms that make the assumptions that qubits are perfect and implies these “perfect qubits, also called logical qubits, will be made of more physical qubits to enable quantum error correction.”
Following these first scientific demonstrations it’s now up to electrical engineers and physicists to work together to turn these demonstrations into practical machines, she said.
“Structuring cooperation takes the effort to build integrated multidisciplinary teams with a common vocabulary,” “To get started, it can be done by determining a set of shared specifications and decide what information is relevant to share with each other and how,” Vinet explained.
Silicon qubits are seen as a serious contender to enable large-scale quantum computing and to implement the algorithms needed to create life-changing applications, the paper concludes. Academic research also is providing insights into the relevant challenges to be overcome. “But it’s now the time for VLSI technologies with more constraints and less versatility but of higher quality, with higher yield and more reproducibility, to address them and provide solutions.”
“FDSOI technology with its backgate provides a way to move the charges away from the interfaces in the qubits on one hand and on the other hand to recenter the Vt of transistors in the control electronics at low temperature. It is thus a unique option to design and fabricate high performance quantum systems-on-chip, (and) CEA-Leti, CEA-IRIG, CNRS Institut Néel and their spin-off, Siquance, are leveraging these FDSOI capabilities to push the quantum computing state-of-the-art in VLSI technologies,” the paper says.
The estimated value creation for the whole industry is close to $1 billion when full fault tolerant quantum computing is possible.
Paper No. 2. “Methodology for an Efficient Characterization Flow of Industrial Grade Si-Based Qubit Devices”
Addressing the microelectronic industry’s lack of an in-depth, wafer-level characterization process for devices in their actual operation regime of quantum confinement at low temperature, CEA-Leti scientists at IEDM 2022 presented a systematic three-step characterization protocol to efficiently gain knowledge on qubit devices, exploiting up to 300mm automated probers at 300K and 1K.
“On-going efforts in scaling-up solid-state spin qubits are hindered by the need for a characterization workflow that assesses the correct device operation at low temperature, and for the associated quality and variability metrics,” “We present here our fast characterization methodology for qubit devices, and present wafer-level (WL) measurements on qubit-array structures at both 300K and 1K. Transistor-like metrics and material characterization provide feedbacks to process integration. They must be enriched by WL measurements at 1K that contain specific information about the electron confinement in a quantum dot. As such, they are crucial for process evaluation as well as device screening before continuing to mK characterization,” the paper reports.
In the race for quantum computing, researchers are pursuing various platforms aiming at quantum bits with greater quality and quantity. Among these, Si-spin qubits stand out due to their long electronic spin coherence times and the potential benefits from the microelectronics industry know-how for both scaling-up and co-integration with classical electronics.
“But researchers don’t have an in-depth, wafer-level characterization process of devices in their actual operation regime of quantum confinement (at low temperature). This capabilitry is crucial for process-and-layout optimization towards improved qubit performance,” said P.-A. Mortemousque, an author of the paper.
The three-step characterization protocol includes:
- 300K “transistor-like” metrics informative on material quality and process variability,
- 1K quantum dot metrics in the many-electron regime and
- qubit metrics at 100mK in the few-electron regime.
The team compared the 300K and 1K metrics of spin-qubit devices on 300mm wafers representing different technological choices for multi-qubit devices, to support the necessity and interest of the three steps.
“This work used for the first time wafer-level quantum dot metrics to evaluate our technology,” Mortemousque said.
Paper No. 3, Invited
“FDSOI for cryoCMOS Electronics: Device Characterization Towards Compact Model”
CEA-Leti reported at IEDM 2022 that it has developed a strategy to perform electrical characterization at a large range of temperatures down to ultra-low temperature, along with electrical characterization methodologies, such as DC, RF, ultra-fast measurements and high statistics.
The strategy has been applied to FDSOI transistors, demonstrating the technology’s high and unique potential for cryogenic applications. Extensive analytical models also have been developed in the first steps toward a full cryogenic compact model that soon will be available for designers to optimize their circuits in an industrial platform, i.e. 28nm FDSOI.
“This work enables a very comprehensive understanding of FDSOI transistor behavior down to ultra-low temperature, which should lead to a breakthrough in cryogenic compact modeling,” said Mikael Cassé, lead author of the invited paper. “This approach already has allowed us to optimize the design of FDSOI cryogenic circuits and most of the results can be easily extended to other advanced technologies, including FinFETS.”
The paper reports that wide range of cryogenic applications, such as spatial, high-performance computing and high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperature.
“More recently, quantum computing has renewed the interest for cryoelectronics with the need of read-out and control electronics in the vicinity of the qubits, pushing the operation temperature of MOSFETs towards 4.2 K and well below. In addition to the gain in main electrical performances owing to the low temperature, cryogenic temperature also favors the emergence of new physical phenomena with possible impact on transistor operation,” according to the paper.
Designers use compact models to conceive their circuits in a given technology. CEA-Leti’s compact model, which is specific to each CMOS technology, ensures that the circuit will operate exactly as the designer wants. Without compact models, designers have to take margins, and make choices in terms of transistors’ dimensions, polarization and other factors that cannot be checked by simulation before the actual fabrication of the circuit.
Potential applications of cryoelectronics go beyond the quantum computing domain. High-performance computing, for example, can exploit the progress in cryogeny to improve processor performance when operating in the 20K-77K range. Low-temperature sensor electronics for spatial applications, high-energy physics experiments and other uses also can benefit from improved cryoelectronics.
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