Alphawave Semi to Showcase Generative AI Innovations at EE Times Seminar
Join Alphawave Semi for a Free Live-Streamed Event to Explore Opportunities Enabled by Chiplet-Based Systems.
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Alphawave Semi has announced three of its technical experts, including its CTO Dr. Tony Chan Carusone, will give presentations and take part in a panel discussion at this week’s EE Times/Embedded.com seminar “Chiplets: Building the Future of SoCs.”
Beginning July 24, and live-streamed on chiplets.eetimes.com, the two-day free event seeks to advance the understanding of engineers, researchers and developers on the potential opportunities and the realities of working with and building chiplet-based systems. Hosted and moderated by Embedded.com’s Editor in Chief, Nitin Dahad, and EE Times’ Senior Reporter covering AI, Sally Ward-Foxton, it will bring together many of the industry’s leading voices, including Cadence, Intel, Synopsys, and Alphawave Semi.
In his tutorial, Chan Carusone will examine how advanced chiplet architectures are enabling breakthroughs in AI. This will include outlining the advances needed across the ecosystem as computation speeds accelerate beyond teraflops, including the importance of UCIe interfaces with a roadmap to 10 Tbps/mm, and delving deeper to show how the migration to chiplets can enable the cost and power efficiencies needed to make AI more sustainable.
Additionally, Mohit Gupta, Alphawave Semi’s SVP and GM of custom silicon and IP, will join a panel discussion moderated by Dahad to examine the state of the commercial chiplet ecosystem. Gupta will be joined by Achronix, Eliyan and Synopsys to discuss the move to multi-supplier ecosystems and the core challenges faced in this transition: Cost, conformity, and supply chain complexity; as well as how to ensure this migration benefits all parties across the ecosystem.
Finally, Letizia Giuliano, Alphawave Semi’s VP of IP Product Marketing, will deliver a technical presentation on UCIe-enabled chiplet IP for AI systems. This will include an analysis of the obstacles in developing interoperable 112G multi-lane and multi-standard chiplets. Giuliano will also examine solutions for scale-up and scale-out connectivity options to meet the networking bandwidth demands of future AI systems.
How to view the presentations
All panel discussions and presentations will be streamed live for free following registration.
Mohit Gupta’s panel debate “Taming Complexity – Building a Successful Open Chiplet Ecosystem” with Achronix, Eliyan and Synopsys will take place on July 24 at 7:40 p.m. CEST (6:40 p.m. UK, 1:40 p.m. Eastern, 10:40 a.m. Pacific).
Letizia Giuliano’s presentation “Optimizing Next-Gen I/O Chiplet: Pioneering UCIe D2D Interconnects from 1.6 Terabits to 224 Gigabits” will take place on July 24 at 8:30 p.m. CEST (7:30 p.m. UK, 2:30 p.m. Eastern, 11:30 a.m. Pacific).
Dr. Tony Chan Carusone’s tutorial “Unleashing AI Potential Through Advanced Chiplet Architectures” will take place on July 25 at 9:15 p.m. CEST (8:15 p.m. UK, 3:15 p.m. Eastern, 12:15 p.m. Pacific).
To register for free, and to see the event’s full agenda visit chiplets.eetimes.com.
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