Synopsys Collaborates with AMD on Instinct MI455X GPU

AMD utilized Synopsys’ 3DIC Compiler platform to construct, implement, and sign off the advanced packaging architecture for the AMD Instinct MI455X GPU. The collaboration covered multi-die co-design, multiphysics analysis, memory interface IP, emulation, and software stack validation for the new GPU series.

Multi-Die Advanced Packaging and Multiphysics Analysis
AMD used Synopsys 3DIC Compiler as an exploration-to-signoff platform for multi-die and advanced package co-design. The platform provided an integrated flow that enabled heterogeneous integration, partitioning, prototyping, floorplanning, and automated die-to-die and die-to-package routing.

The platform's integrated multiphysics analysis and quality-of-results optimization were used to address system-level thermal, power, and electromagnetic constraints across the multi-die assembly. Additionally, AMD integrated Synopsys memory interface IP technologies to manage data movement and bandwidth requirements for the MI455X platform.

Emulation, Hardware Validation, and Verification Software
To accelerate system validation and software readiness prior to physical silicon availability, AMD deployed Synopsys ZeBu emulation systems. The emulation environment supported early validation at the IP and sub-system levels, while enabling software stack development and validation for the SoC.

AMD utilized ZeBu's save-and-restore features to parallelize workflows during debug phases. High-fidelity models on the emulation system executed performance validation workloads to provide feedback on system bottlenecks. Joint engineering between AMD and Synopsys ZeBu teams optimized interfaces between ZeBu software and the AMD Vivado Design Suite to deliver high-capacity emulation models supporting up to 20 billion gates.

For functional verification, AMD deployed Synopsys VC Formal, VCS RTL simulation, and VC LP low-power verification solutions. These tools were applied across both die-level and SoC-level environments to detect bugs, validate low-power design intent, and expand verification coverage.

Cloud Infrastructure Integration
In related cloud computing infrastructure developments, Microsoft announced Azure HXv2, a high-performance computing platform powered by 6th Gen AMD EPYC processors. Developed in collaboration with Synopsys, Azure HXv2 is designed to scale electronic design automation (EDA) workloads and expand capacity for semiconductor design execution.

Edited by Romila DSilva, Induportals Editor, with AI assistance.