Next-Generation 3D Memory Architectures for AI Data Infrastructure

This product announcement details the recent unveiling by Samsung Electronics of its latest 3D memory technologies, designed to enhance the physical architecture of semiconductor memory for artificial intelligence applications. The new solutions, including zHBM and 400-layer NAND, target both large-scale AI data centers and on-device computing by shortening the physical distance between processors and memory.

Architectural Shifts in AI Memory Infrastructure
As artificial intelligence shifts toward complex agentic models requiring extensive reasoning chains, the volume of data stored in caches and passed to accelerators has expanded significantly. The core competitiveness of an AI infrastructure relies heavily on efficient data storage and rapid, reliable delivery to processors. To address this bottleneck, Samsung Electronics redesigned the memory architecture, altering the interface between memory and processor, the chip stacking methodology, and the cell structure itself. These technologies were presented at the Future of Memory and Storage (FMS) 2026 conference, held in Santa Clara, California in August 2026.

Vertical Memory Integration via zHBM Technology
To mitigate the physical limitations of transferring vast datasets, the zHBM architecture stacks high-bandwidth memory directly on top of the AI accelerator instead of placing it adjacently. By reducing the physical distance data travels, this approach increases data-loading bandwidth and power efficiency. The integration relies on Hybrid Copper Bonding (HCB), a mechanism enabling precise copper-to-copper connections, alongside multi-wafer bonding to fuse multiple wafers into a singular unit. These mechanisms increase signal transfer speeds and lower thermal resistance, providing a more stable thermal environment. In large-scale AI data centers, this architectural adjustment improves the training and inference throughput of large models.

Enhancing On-Device AI with zNAND-O Storage
The expansion of on-device AI requires storage components capable of operating efficiently within heavily constrained physical footprints and power limits. The zNAND-O technology addresses these requirements by utilizing 3D packaging that vertically stacks multiple V-NAND chips using Through-Silicon Vias (TSV). This methodology achieves high storage density alongside elevated data-loading bandwidth. In practical applications such as smartphones and local computing devices, this allows complex AI models to process data natively without transmitting information to external cloud servers, thereby maintaining data privacy and reducing latency.

V10 BV-NAND and Ultra-High Layer Stacking
Fitting expanding datasets into standardized physical footprints requires increasing the density of memory cells. The V10 BV-NAND represents a structural evolution, exceeding 400 vertical layers to maximize data capacity. This density is achieved through a specialized bonding architecture. Rather than manufacturing memory cells and peripheral circuits on a single wafer, the V10 BV-NAND process fabricates them on two separate wafers before bonding them precisely. This separation bypasses structural limitations common to ultra-high stacking, yielding a measured 58 percent increase in memory density compared to the previous generation (V9). By utilizing a distinct fabrication process for peripheral circuitry, power consumption during operation is minimized. Within data center environments, these SSD storage components reduce overall power draw and thermal output while maximizing rack density.

Additional Context:
This section details technical specifications and competitive benchmarking not included in the original product announcement

Within the high-bandwidth memory sector, the shift from adjacent interposer placement to direct vertical stacking represents a significant industry transition. Samsung projects its zHBM architecture will deliver approximately eight times the performance and more than ten times the memory density of standard HBM5 configurations, while cutting thermal resistance by more than half, yielding up to three times the performance per watt. While competitors such as SK Hynix and Micron supply substantial volumes of conventional HBM for AI workloads, Samsung is positioning zHBM as a direct structural alternative to mitigate interposer footprint constraints.

In the non-volatile storage market, the V10 BV-NAND is noted as the industry's first announced 400-plus-layer NAND utilizing wafer bonding technology. While competitors like SK Hynix, Micron, and Kioxia operate roadmaps targeting 400-plus layers, the V10 BV-NAND establishes a verified 58 percent density baseline over the previous V9 generation. This metric sets an initial objective standard for volumetric storage efficiency in upcoming enterprise solid-state drives before mass production timelines for competing 400-layer products are fully materialized.

Edited by Natania Lyngdoh, Induportals editor, assisted by AI.

www.semiconductor.samsung.com