Infineon Sets AI Power Delivery Benchmark with Dual-Phase Stages
The compact power stages exceed 2 A/mm² to support high-current AI accelerators and vertical power architectures.
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Infineon Technologies has introduced the TDA235E5 and TDA235E0, a new family of dual-phase smart power stages engineered to address the escalating power density demands of next-generation artificial intelligence accelerators and data center servers. Integrating OptiMOS™ 6 MOSFETs and an advanced dual-phase driver IC into a 6 x 6 x 0.8 mm³ footprint, the devices achieve an industry benchmark current density exceeding 2 A/mm². With support for up to 300 A peak current and 120 A total design current (TDC), the components deliver the high current capacity and compact dimensions necessary to alleviate severe power delivery bottlenecks in modern computing infrastructure.
The power stages support both traditional lateral and emerging vertical power delivery (VPD) topologies. To accommodate the intense thermal loads of advanced compute clusters, the devices feature optimized junction-to-top thermal impedance, facilitating direct integration with liquid-cooling cold plates. When paired with Infineon’s digital multiphase controllers, the power stages enable scalable multi-rail configurations across the broader AI power chain—spanning silicon, silicon carbide (SiC), and gallium nitride (GaN) technologies. Engineering samples of both devices are currently available for customer evaluation.
Additional Context
This section provides technological and market background not explicitly detailed in the original release.
Modern high-performance AI processors (xPUs) and GPUs are pushing socket power demands well past 1,000 watts at core operating voltages below 1 volt, requiring current delivery in excess of 1,000 amperes. In conventional lateral power delivery, voltage regulator modules (VRMs) sit on the perimeter of the processor substrate. This layout forces massive currents through extended motherboard copper traces, leading to substantial resistive losses (I2R), severe voltage drops (IR drop), and board congestion that interferes with high-speed memory and interconnect routing. The transition toward Vertical Power Delivery (VPD)—where power stages and magnetic components are mounted directly beneath the processor socket or on an interposer layer—slashes power distribution track lengths by up to 90%. To make vertical mounting physically viable, smart power stages require extreme power density, ultra-low profiles, and top-side cooling compatibility to channel heat away through custom cold plates, ensuring maximum conversion efficiency and system stability under intense AI workloads.
Edited by Lekshman Ramdas, Induportals editor – adapted by AI.
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